Higher speed, higher density, optimized size and multi-functionality are the main drivers in the evolution of electronic devices. 3D stacked structures are important to meet future demands in the assembly of microprocessors, memory components, image sensors or IR sensors.
Proper interconnection technologies depend on various requirements, such as small form factor, fine pitch, thermal, electrical and mechanical stability. In order to handle a high bump count, tighter pitches and low standoff height, a precise flip-chip bonder capable of high placement accuracy, high bond force and co-planar placement is mandatory.
What are the Challenges?
- Ensure required post bond accuracy of 1-3 micron
- Provide high bond forces of up to 1000 N
- Co-planar placement even with spherical surfaces (bump to bump)
- Establish proper electrical contact on hundreds of thousands of I/O's
- Cope with fine pitch, very small bump diameter and low standoff height
- Bonding of pre-underfilled die
3D Integration Technologies
Thermo Compression with Pre-Underfiller
As underfilling very thin (< 100 µm) or stacked dies is not trivial, pre-underfillers or Non-Conductive Foils (NCF) applied to the wafer before dicing become increasingly popular. This means that during the bonding process, a specific force and temperature is required to liquefy and subsequently activate the underfill material.
Solid Liquid Interdiffusion Bonding (SLID)
Transient Liquid Phase Bonding (TLPB) / Solid Liquid Interdiffusion Bonding (SLID) become increasingly important especially in multi-chip assembly. A low-fusing solder layer between two high-fusing metals is heated, thus generating an inter-metallic phase with a melting point higher than the one of the low-fusing solder. This renders these technologies ideal for multi-stage temperature processes or applications in high temperature environments.
Thermocompression Bonding (Metal-to-Metal)
Metal to Metal Bonding is a good choice for chip packaging and especially image sensors, due to the "mainstream" material being copper. High electrical and thermal conductivity are the main advantages of this material. Via Cu-Cu-Thermo-Compression-Bonding, it is possible to also benefit from these features when it comes to the interconnection of chip and substrate.
Whitepaper: Evaluation Report 3D Packaging Technologies on FINEPLACER® sigma
Tougher requirements related to the request for smaller, lighter and multi-functional electronic devices impose increased demands on IC packagings. Ever more complex circuitry, fine pitch and micro bump designs and die stacking are examples of how the industry meets these demands.
Finding a suitable process technology for 3D packaging can be a challenge. This paper provides information about various connection methods predominantly used in today's 3D packaging.
In comprehensive trials, various dies characterized by high bump count (up to 143,000), fine pitch (down to 25 µm) and small bump diameter (down to 13 µm) was placed on a substrate using a FINEPLACER® sigma. This whitepaper describes test procedures for different 3D integration technologies and presents utilized process parameters and results.